Method for Stacking Devices and Structure Thereof

ABSTRACT

A semiconductor device that has a first device that includes a first through-silicon via (TSV) structure, a first coating material disposed over the first device, the first coating material continuously extending over the first device and covering the first TSV structure, a second device disposed over the first device and within the first coating material, the second device includes a second TSV structure and a plurality of conductive bumps, the plurality of conductive bumps are positioned within the first coating material, a second coating material disposed over the second device, the second coating material continuously extends over the second device and covers the second TSV structure, and a third device disposed over the second coating material, the third device includes a third TSV structure.

PRIORITY DATA

The present application is a divisional application of U.S. patentapplication Ser. No. 12/163,464, filed Jun. 27, 2008, which isincorporated herein by reference in its entirety.

BACKGROUND

The present disclosure relates generally to semiconductor manufacturingand, more particularly, to a method for fabricating a stackedsemiconductor device.

Vias have been routinely used in semiconductor fabrication to provideelectrical coupling between one or more layers of conductive materialwithin a semiconductor device. More recently, through-silicon vias (TSV)have arisen as a method of overcoming limitations of conventional wirebonding for example, as performance and density requirements increase nolonger allowing traditional wire bonding to be adequate. TSV allow forshorter interconnects by forming an interconnect in the z-axis. Theinterconnect is created through a substrate (e.g. wafer), by forming avia extending from a front surface to a back surface of the substrate.TSV are also useful in forming interconnects for stacked wafers, stackedchip, and/or combinations thereof for 3-D packaging technologies.

In fabricating stacked semiconductor devices, a liquid no-flow underfill(NFU) including a flux is typically used for stacking and coupling twodevices. The NFU layer is subjected to a thermal process (e.g.,curing/reflow cycle) in which the NFU layer is cured and encapsulatesthe structures in a region between the devices. Also, solder bumps ofone of the devices are reflowed and form a solder joint with TSVstructures of the other device such that the devices become electricallycoupled. For each additional device that is to be stacked and coupled,an additional NFU layer is provided and the thermal process is repeated.Although this method has been satisfactory for its intended purpose, ithas not been satisfactory in all respects. One of the disadvantages isthat the lower NFU layers are subjected to many curing/reflow cyclesduring the fabrication of stacked semiconductor device. This mayincrease the thermal stress of the NFU layer, and may induce variousdefects such as voids in the NFU layer, bump cracks or fracture, andpeeling of the NFU layer, and thus may lead to poor device performanceand reliability.

Therefore, a need exists for a method for fabricating a stackedsemiconductor device that reduces the thermal stress of the coatingmaterial between devices.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isemphasized that, in accordance with the standard practice in theindustry, various features are not drawn to scale. In fact, thedimensions of the various features may be arbitrarily increased orreduced for clarity of discussion.

FIGS. 1A to 1G, illustrated are cross sectional views of a stackedsemiconductor device at various stages of fabrication;

FIG. 2, illustrated is a cross sectional view of a stacked semiconductordevice with various defects that may be induced during fabrication;

FIG. 3, illustrated is a flowchart of a method for fabricating a stackedsemiconductor device according to various aspects of the presentdisclosure;

FIGS. 4A to 4E, illustrated are cross-sectional views a stackedsemiconductor device at various stages of fabrication according to themethod of FIG. 3;

FIG. 5, illustrated is a flowchart of an alternative method forfabricating a stacked semiconductor device according to various aspectsof the present disclosure;

FIGS. 6A to 6F, illustrated are cross sectional views of a stackedsemiconductor device at various stages of fabrication according to themethod of FIG. 5;

FIG. 7, illustrated are cross-sectional views of the stackedsemiconductor device of FIG. 4 being fabricated with an alternativemethod for forming a coating material; and

FIGS. 8A and 8B, illustrated are cross-sectional views of the stackedsemiconductor device of FIG. 6 being fabricated with an alternativemethod for forming a coating material.

DETAILED DESCRIPTION

The present disclosure relates generally to semiconductor manufacturingand more particularly, to a method for fabricating a stackedsemiconductor device. It is understood, however, that specificembodiments are provided as examples to teach the broader inventiveconcept, and one of ordinary skill in the art can easily apply theteaching of the present disclosure to other methods or devices. Inaddition, it is understood that the methods and apparatus discussed inthe present disclosure include some conventional structures and/orprocesses. Since these structures and processes are well known in theart, they will only be discussed in a general level of detail.

Furthermore, reference numbers are repeated throughout the drawings forsake of convenience and example, and such repetition does not indicateany required combination of features or steps throughout the drawings.Moreover, the formation of a first feature over, on, adjacent, abutting,or coupled to a second feature in the description that follows mayinclude embodiments in which the first and second features are formed indirect contact, and may also include embodiments in which additionalfeatures may be formed interposing the first and second features, suchthat the first and second features may not be in direct contact. Also,the formation of a feature on a substrate, including for example,etching a substrate, may include embodiments where features are formedabove the surface of the substrate, directly on the surface of thesubstrate, and/or extending below the surface of the substrate.

Referring to FIGS. 1A to 1G, illustrated are cross sectional views of astacked semiconductor device 100 at various stages of fabrication. InFIG. 1A, the semiconductor device 100 may include a first level device102 having a circuit. Accordingly, the device 102 may comprise asubstrate 104 that includes one or more features formed on thesubstrate. These features are not illustrated but may be present on thesubstrate 104, and may include, for example, gate structures,source/drain regions, other doped regions, isolation structures,contacts to one or more of the gate, source, or drain regions, memoryelements (e.g., memory cells), and/or other features known in the art.The device 102 may further include one or more metal layers andinter-layer dielectric (collectively referred to as interconnectstructure) formed on the front surface 106 of the substrate 104. Thedevice 102 may further include one or more contact pads that provideelectrical contact to the interconnect structure.

The device 102 may further include a plurality of through-silicon via(TSV) structures 108 formed on and in the substrate 104. The TSVstructures 108 may be vertical conductive structures that pass throughthe substrate 104. Also, the TSV structures 108 may be electricallycoupled to the contact pads, and electrically coupled to theinterconnect structure. The TSV structures 108 may be exposed from theback surface 110 of the substrate 104 for 3-D packaging such as stackingand coupling to other devices as will be discussed later herein. Thedevice 102 may further include a plurality of bonding pads 112 that areelectrically coupled to the interconnect structure, and may supportconductive features such as solder bumps (or balls) for use in flip-chippackaging technology and other suitable packaging technologies.

The device 102 may be secured to a vacuum plate 120 that is capable ofproviding a vacuum suction force 122, 124. The vacuum plate 120 may alsoprovide a stable base support for stacking a number of devices to formthe stacked semiconductor device 100. The vacuum plate 120 may include asupport plate 126 with a buffer layer formed thereon for supporting anarea of the front surface 106 of the device 102 that includes variousstructures such as bonding pads 112. Accordingly, these variousstructures on the front surface 106 of the device 102 are protected frombeing damaged during the stacking process. The area of the front surface106 of the device 102 that does not include external structures has asubstantially flat surface, and may be well suited for securing to thevacuum plate 120 via the suction force 122, 124. Alternatively, thedevice 102 may optionally be secured to a carrier substrate with anadhesive material.

A layer 130 of a liquid no-flow underfill (NFU) may be formed on theback surface 110 of the device 102. The NFU may function as both a lowviscosity liquid epoxy material for encapsulating, and a flux componentfor reflowing. The layer 130 of NFU may be applied (referred to as NFUprinting) to the back surface 110 by a dispenser 132. It should be notedthat “front” and “back” such as the front surface of the substrate andthe back surface of the substrate, as used herein are arbitrary and thesurfaces of the substrate may be referenced by any suitable convention.

In FIG. 1B, the semiconductor device 100 may include a second leveldevice 140 with a circuit. Accordingly, the device 140 may include asubstrate 142 having various features (similar to the features discussedin device 102) that function as the circuit, a plurality of bonding pads143 and micro bumps 144 formed on the front surface 145 that areelectrically coupled to the circuit, and a plurality of TSV structures146 that extend through the substrate and may be exposed from the backsurface 147. The device 140 may be placed overlying the layer 130 andthe device 102 such that the micro bumps 144 are in contact and alignedwith the proper TSV structures 108 of device 102.

In FIG. 1C, the semiconductor device 100 including device 102 and device140 may be transferred to a heating chamber 150 such as an oven, and thesemiconductor device 100 may be heated 155 to a desired temperature orrange of temperatures for a period of time (e.g., curing/reflow cycle).For example, the temperature range may be from 200 to 300° C. Aspreviously noted, the layer 130 includes an epoxy material forencapsulating and a flux component for reflowing. Accordingly,responsive to the heating, the epoxy material fully cures andencapsulates the various structures between the device 102 and thedevice 140. This provides the required mechanical strength and stabilityfor stacking and bonding the device 102 to device 140. Simultaneously,the flux component reflows the micro bumps 144 of device 140, and formsa solder joint with the TSV structure 108 of device 102. As such, thecircuit of device 102 may be electrically coupled to the circuit ofdevice 140.

In FIG. 1D, a layer 160 of a liquid NFU may be formed on the backsurface 147 of the device 140 via the dispenser 132. As previouslynoted, the NFU may function as both a low viscosity liquid epoxymaterial for underfilling or encapsulating, and a flux component forreflowing or soldering. In FIG. 1E, the semiconductor device 100 mayinclude a third level device 170 with a circuit. Accordingly, the device170 may include a substrate 172 having various features (similar to thefeatures discussed in device 102) that function as the circuit, aplurality of bonding pads 173 and micro bumps 174 formed on the frontsurface 175 that are electrically coupled to the circuit, and aplurality of TSV structures 176 that extend through the substrate andmay be exposed from the back surface 177. The device 170 may placedoverlying the layer 160 and the device 140 such that the micro bumps 174are in contact and aligned with the proper TSV structures 146 of device140.

In FIG. 1F, the semiconductor device 100 including device 102, device140, and device 170 may be placed in the heating chamber 150, and thesemiconductor device 100 may be heated 155 to a desired temperature orrange of temperatures for a period of time (e.g., cycle) similar to thethermal process of FIG. 1C. The layer 160 fully cures and encapsulatesthe structures between the device 140 and the device 170, and the fluxcomponent reflows the micro bumps 174 to form a solder joint with theTSV structure 146 of device 140. However, the fully cured layer 130 issubjected to another thermal cycle, and the thermal stress of layer 130may be increased. In FIG. 1G, the process above is repeated for eachadditional device that is to be stacked, and the number of devices maydepend on the application and/or design requirements. After the lastdevice has been stacked and the last layer of NFU layer has been fullycured, the vacuum suction force 122, 124 may be turned off, and thesemiconductor device 100 may be removed from the vacuum plate 120 forfurther processing.

Referring to FIG. 2, illustrated are various defects that may be inducedduring the fabrication of a stacked semiconductor 200. The stackedsemiconductor 200 may be similarly fabricated as was discussed in thestacked semiconductor 100 of FIG. 1. The stacked semiconductor 200 mayinclude a first 201, second 202, third 203, fourth 204, fifth 205, andnth 206 device (where n is the total number of devices being stacked).The device 201 may include a plurality of solder bumps (or balls) 207each formed on a bonding pad 208 for use in flip-chip packagingtechnology or other suitable packaging technologies. The device 201 mayfurther include a plurality of redistribution layer (RDL) structures 209for rerouting bonding pads to various areas of the device 201. Thedevice 201 may further include a plurality of TSV structures 210 forcoupling to other devices in 3-D device packaging and/or device stackingconfigurations.

As previously discussed, a NFU layer 211 (similar to the layer 130 ofFIG. 1) may be dispensed (also referred to as NFU printing) over thedevice 201, and the device 202 may be placed overlying the NFU layer 211and the device 201. The device 202 may include a plurality of microbumps (or balls) 216 each formed on a bonding pad 218 for coupling toone or more TSV structures 210 of device 201. The NFU layer 211 may thenbe subjected to a thermal process to cure the NFU layer 211 and reflowthe micro bumps to electrically couple the devices 201 and 202. Thedevice 202 may further include one or more TSV structures 219 forcoupling to another device in 3-D device packaging and/or devicestacking configurations. The process above is repeated for each of theother devices 203, 204, 205, 206 to form the stacked semiconductordevice 200. Accordingly, the NFU layer 211 may be subjected to (n−1)times of curing/reflow cycles, NFU layer 212 may be subjected to (n−2)times of curing/reflow cycles, NFU layer 213 may be subjected to (n−3)times of curing/reflow cycles, NFU layer 214 may be subjected to (n−4)times of curing/reflow cycles, and NFU layer 215 may be subjected to(n−5) times of curing/reflow cycles, and so forth. Therefore, each ofthe NFU layers 211-215 may have a different thermal history or cyclethan the others, with the NFU layer 211 having the longest thermal cycleand the NFU layer 215 having the shortest thermal cycle (e.g., for n=6total devices).

It has been observed that various defects may be induced with theincrease in the thermal history or cycle of the NFU layer. That is, thelonger or more times the NFU layer is subjected to thermal processing(e.g., curing/reflow cycles), the more likely defects will be induced bythermal stress experienced in the NFU layer. For example, the NFU layer211 may have the longest thermal cycle, and the defects that may beinduced include a bump crack or fracture 220 in which the micro bump maybe separated from the bond pad, voids 222, 224, 226, 228 in the NFUlayer 211, and delaminating or peeling 229 occurring at the interface ofthe NFU layer 211 and micro bumps 216. The NFU layer 212 may have thesecond longest thermal cycle, and thus similar defects may be inducedsuch as laminating or peeling 230, and voids 234, 236, 238 in the NFUlayer 212. The NFU layer 213 may have the third longest thermal cycle,and thus may induce defects such as voids 240, 242 in the NFU layer 213.The NFU layer 215 may have the shortest thermal cycle that includes onecuring/reflow cycle, and thus may have substantially no or very fewdefects induced by thermal stress. However, the NFU layer 215 is a lowviscosity liquid before being fully cured, and thus some defects such asvoids may develop even after one curing/reflow cycle. These variousdefects can lead to poor device performance and reliability.

For the sake of example, an example device will be shown below in aseries of processing operations to illustrate various embodiments of thepresent invention. It is understood that several processing steps may beonly briefly described, such steps being well known to those of ordinaryskill in the art. Also, additional processing steps can be added, andcertain of the following processing steps can be removed and/or changedwhile still implementing the claimed invention. Thus, the followingdescription should be understood to represent examples only, and are notintended to suggest that one or more steps is required. It shouldfurther be noted that “front” and “back” such as the front surface ofthe substrate and the back surface of the substrate, as used herein arearbitrary and the surfaces of the substrate may be referenced by anysuitable convention.

Referring to FIG. 3, illustrated is a method 300 for fabricating astacked semiconductor device that utilizes one curing/reflow cycle.Referring also to FIGS. 4A to 4E, illustrated are cross sectional viewsof a stacked semiconductor device 400 being fabricated according to themethod 300 of FIG. 3. In FIG. 4A, the method 300 begins with block 302in which a first level device 402 may be provided with a first coatingmaterial 404 formed thereon.

The coating material 404 may be formed by applying a lamination or tape406 having a polymer component and a flux component. The coatingmaterial 404 may include an epoxy polymer that is configured as a highviscosity solid film. Accordingly, the coating material 404 may havesufficient mechanical strength and stability to hold a device in placebefore the material is later fully cured. Alternatively, the coatingmaterial 404 may optionally be formed by a spin-coating process. Forexample, the coating material 404 may include a liquid epoxy polymerwith a flux component that is applied to the device 402, and the coatingmaterial 404 may be subjected to a pre-treatment process. In thepre-treatment process, the coating material 404 may be heated to atemperature that is less than a curing temperature of the coatingmaterial 404. For example, the coating material 404 may be heated to atemperature from about 80 to about 150° C. The heating may include aheat source such as a flash lamp, ultraviolet illumination, or othersuitable heating mechanisms. Accordingly, the coating material 404 maybe transformed from a liquid to a B-stage polymer (e.g., intermediatestage between liquid and fully cured polymer), such that the viscosityof the coating material is increased. Thus, the coating material 404 mayhave sufficient mechanical strength and stability to hold a device inplace before the material is later fully cured. Further, the coatingmaterial 404 may include a promoter for increasing the adhesiveproperties of the coating material 404, and other additives forenhancing the curing of the coating material 404.

The device 402 may include a circuit formed in a semiconductor substrate410 such as a silicon in a crystalline structure. Alternatively, thesubstrate 410 may have an epitaxial layer overlying a bulksemiconductor. Further, the substrate 410 may be strained forperformance enhancement. For example, the epitaxial layer may comprisesemiconductor materials different from those of the bulk semiconductorsuch as a layer of silicon germanium overlying a bulk silicon, or alayer of silicon overlying a bulk silicon germanium formed by a processincluding selective epitaxial growth (SEG). Furthermore, the substrate410 may include a semiconductor-on-insulator (SOI) structure. Forexample, the substrate 410 may include a buried oxide (BOX) layer formedby a process such as separation by implanted oxygen (SIMOX). Thesubstrate 410 may include various doped wells, doped features, andsemiconductor layers configured to form various microelectronic devicessuch as metal-oxide-semiconductor field effect transistor (MOSFET)including complementary metal-oxide-semiconductor (CMOS), imaging sensorincluding CMOS imaging sensor (CIS), micro-electro-mechanical system(MEMS), memory cells, and/or other suitable active and passive devices.The substrate 410 may also include various isolation features configuredto separate different devices formed on the substrate. The isolationfeatures may include different structures and can be formed usingdifferent processing technologies. For example, the isolation featuresmay include dielectric isolation features such as shallow trenchisolation (STI). The doped wells and doped features include p-type dopedregion and/or an n-type doped region, formed by a doping process such asion implantation.

The device 402 may further include an interconnect structure with one ormore metal layers that are configured to connect various doped regionsand/or features in the semiconductor substrate 410, resulting in thefunctional circuit. The interconnect structure may include conductivematerials such as copper, copper alloy, titanium, titanium nitride,tantalum, tantalum nitride, tungsten, polysilicon, metal silicide, orcombinations. The copper interconnect may be formed by a technique suchas CVD, sputtering, plating, or other suitable processes. Alternativelyor additionally, an aluminum interconnect may be used and include analuminum, aluminum/silicon/copper alloy, titanium, titanium nitride,tungsten, polysilicon, metal silicide, or combinations. The aluminuminterconnect may be formed by a process including physical vapordeposition (or sputtering), chemical vapor deposition (CVD), orcombinations thereof. Other manufacturing techniques to form thealuminum interconnect may include photolithography processing andetching to pattern the conductive materials for vertical (via andcontact) and horizontal connects (conductive line).

The interconnect structure may include an inter-layer dielectric with alow dielectric constant such as less than about 3.5. The dielectric mayinclude silicon dioxide, silicon nitride, silicon oxynitride, polyimide,spin-on glass (SOG), fluoride-doped silicate glass (FSG), carbon dopedsilicon oxide, Black Diamond® (Applied Materials of Santa Clara,Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB(bis-benzocyclobutenes), SiLK (Dow Chemical, Midland, Mich.), and/orother suitable materials. The dielectric may be formed by a techniqueincluding spin-on, CVD, sputtering, or other suitable processes. Themetal layers and inter-layer dielectric may be formed in an integratedprocess such as a damascene process or lithography/plasma etchingprocess.

The device 402 may include a plurality of bonding pads 412 forsupporting solder bumps (or balls) and other external bonding mechanismsfor use in flip-chip packaging technology and other suitable packagingtechnologies. The device 402 may further include a plurality ofredistribution layer (RDL) structures (not shown) for rerouting thebonding pads to various areas of the device 402. The bonding pads 412may be formed within a passivation layer overlying the top metal layeron the front surface 413 of the substrate 410, and may be electricallycoupled to the interconnect structure. The device 402 may furtherinclude a plurality of through-silicon via (TSV) structures 414. The TSVstructures 414 may be vertical conductive structures that pass throughthe substrate 410, and may be electrically coupled to the interconnectstructure and/or the bonding pads 412. The TSV structures 414 may beexposed from the back surface 415 of the substrate 410 for 3-D packagingsuch as stacking and coupling to other devices as will be discussedlater herein. Such TSV 3-D packaging creates vertical connectionsthrough the substrate body, eliminates additional wires, and produces aflatter and more compact structure.

The device 402 may be secured to a vacuum plate 420 that is capable ofproviding a vacuum suction force 422, 424. The vacuum plate 420 may alsoprovide a stable base support for stacking a number of devices to formthe stacked semiconductor device 400. The vacuum plate 420 may include asupport plate 426 with a buffer layer formed thereon for supporting anarea of the front surface 413 of the device 102 that includes variousstructures such as bonding pads 412. Accordingly, these variousstructures on the front surface 413 of the device 402 are prevented frombeing damaged during the stacking process. The area of the front surface413 of the device 402 that does not include external structures has asubstantially flat surface, and may be well suited for securing to thevacuum plate 420 via the suction force 422, 424. Alternatively, thedevice 402 may optionally be secured to a carrier substrate with anadhesive material.

In FIG. 4B, the method 300 continues with block 304 in which a secondlevel device 430 may be placed overlying the first coating material 404and the first level device 402. The device 430 may include a secondcoating material 431 formed thereon. The coating material 431 may besimilar to the coating material 404, and may be formed in a similarmanner as discussed above. Also, the coating material 431 may bepre-laminated on the device 430 prior to being placed over the device402, reducing processing time. The device 430 may further include asubstrate 432 having various features (similar to the features discussedin device 402) that function as a circuit, a plurality of bonding pads433 and micro bumps 434 formed on the front surface 435 that areelectrically coupled to the circuit via an interconnect structure, and aplurality of TSV structures 436 that extend through the substrate 432and may be exposed from the back surface 437. The TSV structures 436 maybe electrically coupled to the interconnect structure and/or bondingpads 433. A sufficient amount of force may be applied to the device 430such that the front surface 435 contacts and adheres to the coatingmaterial 404. Further, the micro bumps 434 of device 430 may be alignedwith the proper TSV structures 414 of device 402, and positionedproximate to or in contact with the TSV structures 414 for reflowing themicro bumps 434.

Alternatively, referring also to FIG. 7, the coating material 404 mayoptionally be formed on the front surface 435 of device 430 instead ofbeing formed on the back surface 415 of device 402 prior to stacking.Accordingly, the device 430 with the coating material 404 may be flippedover 702 and stacked on the device 402. A sufficient amount of force maybe applied to the device 430 such that the front surface 415 of device402 contacts and adheres to the coating material 404. Further, the microbumps 434 of device 430 may be aligned with the proper TSV structures414 of device 402, and positioned proximate to or in contact with theTSV structures 414 for reflowing the micro bumps 434.

In FIG. 4C, the method 300 continues with block 306 in which a thirdlevel device 440 may be placed overlying the second coating material 431and the second level device 430. The device 440 may include a thirdcoating material (not shown) formed thereon for stacking another device.The device 440 may further include a substrate 442 having variousfeatures (similar to the features discussed in device 402) that functionas a circuit, a plurality of bonding pads 443 and micro bumps 444 formedon the front surface 445 that are electrically coupled to the circuitvia an interconnect structure, and a plurality of TSV structures 446that extend through the substrate 442 and may be exposed from the backsurface 447. The TSV structures 446 may be electrically coupled to theinterconnect structure and/or bonding pads 443. A sufficient amount offorce may be applied to the device 440 such that the front surface 445contacts and adheres to the coating material 431. Also, the micro bumps444 of device 440 may be aligned with the proper TSV structures 436 ofdevice 430, and positioned proximate to or in contact with the TSVstructures 436 for reflowing the micro bumps 444.

It should be noted that the coating material 431 may optionally beformed on the front surface 445 of device 440 instead of being formed onthe back surface 437 of device 430 prior to stacking, as was similarlydiscussed above in FIG. 7. Accordingly, subsequent coating materials maybe formed in a similar manner for stacking additional devices to formthe stacked semiconductor device 400.

The process above may be repeated for each additional device that is tobe stacked, and the number of devices may vary depending on the designrequirements of the stacked semiconductor device 400. It should be notedthat only three devices are described for the sake of clarity and abetter understanding of the disclosed embodiments. In FIG. 4D, after thelast device has been stacked, the method 300 continues with block 308 inwhich the coating materials 404, 431 may be cured in the same thermalprocess. The semiconductor device 400 may be transferred to a heatingchamber 450 such as an oven, and the semiconductor device 400 may beheated 455 to a desired temperature or range of temperatures for aperiod of time (e.g., curing/reflow cycle). For example, the temperaturerange may be from 200 to 300° C. The heating chamber 450 may include aheat source such as a flash lamp, ultraviolet illumination, or othersuitable heating mechanisms. As previously noted, each coating material404, 431 includes an epoxy polymer for encapsulating and a fluxcomponent for reflowing. Accordingly, responsive to the heating, theepoxy polymer fully cures and encapsulates the various structuresbetween the devices 402, 430, and 440, and provides the requiredmechanical strength and stability for stacking and bonding the devices.Simultaneously, the flux component reflows the micro bumps 434, 444, andforms a solder joint with the corresponding TSV structures 414, 436.

Therefore, the circuits of the devices 402, 430, and 440 may beelectrically coupled to each other to form a circuit for the stackedsemiconductor device 400. Accordingly, the coating materials 404, 431are fully cured and the micro bumps 434, 444 are reflowed in the samecuring/reflow cycle, and thus the coating materials 404, 431 may havesubstantially similar thermal histories. This greatly reduces thethermal stress of the coating materials 404, 431 even as the number ofdevices being stacked increases since all the coating materials willstill be subjected to one curing/reflowing cycle. The various defectsinduced by thermal stress as discussed in FIG. 2 may be minimized, andthus the performance and reliability of the semiconductor device 400 maybe improved. Further, since the coating materials 404, 431 may beconfigured as a high viscosity solid film or a B-stage polymer fordevice stacking, voids formed in the coating materials 404, 431 will bereduced as compared to using a low viscosity liquid NFU as discussed inFIG. 2.

Additionally, the semiconductor device 400 may optionally be subjectedto a post-treatment process in a heating chamber to fully crosslink theepoxy polymer of the coating materials 404 and 431. In thepost-treatment process, the semiconductor device 400 may be heated to atemperature range from 100 to about 200° C. The heating chamber mayinclude a heat source such as a flash lamp, ultraviolet illumination, orother suitable heating mechanisms.

In FIG. 4E, after the curing/reflow process, the stacked semiconductordevice 400 may be removed from the vacuum plate 420 by turning off thevacuum suction force 422, 424. The semiconductor device 400 may furtherinclude a plurality of solder bumps (or balls) 460 for use in flip-chippackaging technology, and other suitable packaging technologies. Thedevices 402, 430, 440 may each include a chip (or die), and thus themethod 300 of FIG. 3 may be implemented for chip-to-chip stacking andbonding. Alternatively, the devices 402, 430, 440 may each include awafer, and thus the method 300 of FIG. 3 may be implemented forwafer-to-wafer stacking and bonding.

Referring to Referring to FIG. 5, illustrated is a method 500 forfabricating a stacked semiconductor device. Referring also to FIGS. 6Ato 6F, illustrated are cross sectional views of a stacked semiconductordevice 600 being fabricated according to the method 500 of FIG. 5. Thestacked semiconductor device 600 is similar to the stacked semiconductordevice 400 of FIG. 4 except that the device 600 includes die-to-waferstacking and bonding. Similar features in FIGS. 4 and 6 are numbered thesame for the sake of simplicity and clarity.

In FIG. 6A, the method 500 begins with block 502 in which a wafer 602such as a semiconductor wafer may be provided with a coating material404 formed thereon. The wafer 602 may include various semiconductorfeatures (similar to the features discussed in device 402) that functionas a circuit, a plurality of bonding pads 607 and conductive bumps 608(e.g., Au, Cu, or other suitable conductive material) formed on thefront surface 609 that are electrically coupled to the circuit via aninterconnect structure (not shown). The conductive bumps 608 may be usedin flip-chip packaging technology or other suitable packagingtechnologies. The wafer 602 may further include a plurality ofredistribution layer (RDL) structures (not shown) for rerouting thebonding pads to various areas of the wafer 602. The wafer 602 mayfurther include a plurality of through-silicon via (TSV) structures 610,611, 612 that extend through the wafer 602 and may be exposed from theback surface 613. Each of the TSV structures 610, 611, 612 may be formedin a portion of the wafer 602 for coupling to a plurality of chips asdiscussed below. The TSV structures 610, 611, 612 may be electricallycoupled to the circuit via the interconnect structure, and may beelectrically coupled to the bonding pads and/or other conductivefeatures. Alternatively, the TSV structures 610, 611, 612 may be part ofthe interconnect structure.

The wafer 602 may be secured to a vacuum plate 420 that is capable ofproviding a vacuum suction force 422, 424. The vacuum plate 420 may alsoprovide a stable base support for stacking a number of devices to formthe stacked semiconductor device 600. The vacuum plate 420 may include asupport plate 426 with a buffer layer formed thereon for supporting anarea of the front surface 609 of the wafer 602 that includes variousstructures such as conductive bumps 608. Accordingly, these variousstructures on the front surface 609 of the wafer 602 are prevented frombeing damaged during the stacking process. The area of the front surface609 of the wafer 602 that does not include external structures has asubstantially flat surface, and may be well suited for securing to thevacuum plate 420 via the suction force 422, 424.

In FIG. 6B, the method 500 continues with block 504 in which a pluralityof first level chips 621, 622, 623 may be stacked on the coatingmaterial 404 and the wafer 602. It should be noted the number of firstlevel chips may vary, and that only three chips are shown for the sakeof clarity and better understanding of the disclosed embodiments. Thechips 621, 622, 623 may each include a circuit such as memory cells, anda bump layer 630 (including bonding pads) for electrically coupling tothe corresponding TSV structures 610, 611, 612 of the wafer 602.Accordingly, the circuits of chips 621, 622, 623 may be electricallycoupled to the circuit of wafer 602. The bump layer 630 may includesolder bumps, Au bumps, Cu bumps, or other suitable conductive bumpsknown in the art. Each of the chips 621, 622, 623 may further include aplurality of TSV structures 632 for coupling to other chips as discussedbelow. The chips 621, 622, 623 may be stacked on the wafer 602 by arobotic arm 640 or other suitable mechanism such that the bump layer 630is accurately aligned with the corresponding TSV structures 610, 611,612, and the bump layer 630 is proximate to or in contact with thecorresponding TSV structures for reflowing. Further, the chips 621, 622,623 may be held in place by the coating material 404. The chips 621,622, 623 may further include a coating material 645 formed thereon, thecoating material 645 may be substantially similar as the coatingmaterial 404 and may be formed in a similar manner.

Alternatively, referring also to FIG. 8A, a coating material 802(similar to the coating material 404 in FIG. 6A) may be formed on thefirst level chips 621, 622, 623 instead of being formed on the backsurface 613 of the wafer 602 (in FIG. 6A) prior to stacking the firstlevel chips on the wafer as discussed above in FIG. 6B.

In FIG. 6C, the method 500 continues with block 506 in which a pluralityof second level chips 651, 652, 653 may be stacked on the coatingmaterial 645 and the first level chips 621, 622, 623, respectively. Thechips 651, 652, 653 may each include a circuit such as memory cells, anda bump layer 654 (including bonding pads) for electrically coupling tothe TSV structures 632 of the corresponding first level chips 621, 622,623. Accordingly, the circuits of chips 651, 652, 653 may beelectrically coupled to the circuits of the chips 621, 622, 623,respectively. The bump layer 654 may include solder bumps, Au bumps, Cubumps, or other suitable conductive bumps known in the art. Each of thechips 651, 652, 653 may further include a plurality of TSV structures656 for coupling to other chips as discussed below. The chips 651, 652,653 may be stacked on the chips 621, 622, 623 by a robotic arm 640 suchthat the bump layer 654 is accurately aligned with the TSV structures632 of the corresponding chips 621, 622, 623, and the bump layer 654 isproximate to or in contact with the TSV structures for reflowing.Further, the chips 651, 652, 653 may be held in place by the coatingmaterial 645. The chips 651, 652, 653 may further include a coatingmaterial 658 formed thereon, the coating material 658 may besubstantially similar as the coating material 404 and may be formed in asimilar manner.

Alternatively, referring also to FIG. 8B, the coating material 645 maybe formed on the second level chips 651, 652, 653 instead of beingformed on the first level chips 621, 622, 623 (in FIG. 6B) prior tostacking the second level chips on the respective first level chips asdiscussed above in FIG. 6C.

In FIG. 6D, the method 500 continues with block 508 in which a pluralityof top level chips 661, 662, 663 may be stacked on the coating material658 and the chips 651, 652, 653, respectively. It should be noted thenumber of levels may vary depending on the design requirements of thestacked semiconductor device 600, and that only three levels are shownfor the sake of clarity and better understanding of the disclosedembodiments. The chips 661, 662, 663 may each include a circuit such asmemory cells, and a bump layer 664 for electrically coupling to the TSVstructures 656 of the corresponding chips 651, 652, 653. Accordingly,the circuits of chips 661, 662, 663 may be electrically coupled to thecircuits of chips 651, 652, 653, respectively. The bump layer 664 mayinclude solder bumps, Au bumps, or Cu bumps. The chips 661, 662, 663 maynot include TSV structures and coating material since these are the toplevel chips and no other chips will be stacked over them. The chips 661,662, 663 may be stacked by a robotic arm 640 such that the bump layer664 is accurately aligned with the TSV structures 656 of thecorresponding chips 651, 652, 653, and the bump layer 664 is proximateto or in contact with the corresponding TSV structures for reflowing.

Alternatively, referring also to FIG. 8B, the coating material 658 maybe formed on the top level chips 661, 662, 663 instead of being formedon the second level chips 651, 652, 653 (in FIG. 6C) prior to stackingthe top level chips on the respective second level chips as discussedabove in FIG. 6D.

In FIG. 6E, the method 500 continues with block 510 in which the coatingmaterials 404, 645, 658 may be cured in the same thermal process. Thesemiconductor device 600 may be transferred to a heating chamber 450such as an oven, and the semiconductor device 600 may be heated 455 to adesired temperature or range of temperatures for a period of time (e.g.,curing/reflow cycle). For example, the temperature range may be from 200to 300° C. As previously noted, each coating material 404, 645, 658includes an epoxy polymer for encapsulating and a flux component forreflowing. Accordingly, responsive to the heating, the epoxy polymerfully cures and encapsulates the various structures between the chips621-623, 651-653, 661-663, and between the chips 621-623 and wafer 602,and provides the required mechanical strength and stability for stackingand bonding the chips and wafer. Simultaneously, the flux componentreflows the bump layers 630, 654, 664, and forms a electrical joint withthe corresponding TSV structures 610-612, 632, 656.

Accordingly, the coating materials 404, 645, 658 are fully cured and thebump layers 630, 654, 664 are reflowed in the same curing/reflow cycle,and thus the coating materials 404, 645, 658 may have substantiallysimilar thermal histories. This greatly reduces the thermal stress ofthe coating materials 404, 645, 658 even as the number of devices beingstacked increases since all the coating materials will still besubjected to one curing/reflowing cycle. The various defects induced bythermal stress as discussed in FIG. 2 may be minimized, and thus theperformance and reliability of the semiconductor device 600 may beimproved. Further, since the coating materials 404, 645, 658 may beconfigured as a high viscosity solid film or a B-stage polymer fordevice stacking, voids formed in the coating materials 404, 645, 658will be reduced as compared to using a low viscosity liquid NFU asdiscussed in FIG. 2.

Additionally, the semiconductor device 600 may optionally be subjectedto a post-treatment process in a heating chamber to fully crosslink theepoxy polymer of the coating materials 404, 645, 658. In thepost-treatment process, the semiconductor device 600 may be heated to atemperature range from 100 to about 200° C. The heating chamber mayinclude a heat source such as a flash lamp, ultraviolet illumination, orother suitable heating mechanisms.

In FIG. 6F, the method 500 continues with block 512 in which thesemiconductor device 600 may undergo a wafer molding process. A moldingcompound 670, NFU, or other suitable material may be formed partiallysurrounding the semiconductor device 600 for protection and mechanicalstrength. The semiconductor device 600 may be removed from the vacuumplate 420 and may undergo further semiconductor processing.

Thus, provided is a method for fabricating a semiconductor device whichincludes providing a first device, a second device, and a third device,providing a first coating material between the first device and thesecond device, providing a second coating material between the seconddevice and the third device, and thereafter, curing the first and secondcoating materials in a same process. In some embodiments, the first,second, and third devices each include a circuit, the first and seconddevices each include a through silicon via (TSV) structure, and themethod further includes, responsive to the curing, electrically couplingthe circuits of the first, second, and third devices using the TSVstructure of the first and second devices, wherein the first and secondcoating materials both include a flux component that facilitates thecoupling. In some other embodiments, the first, second, and thirddevices are each one of a die and a wafer.

In still other embodiments, the third device includes a third coatingmaterial formed thereon, and the method includes overlying a fourthdevice on the third coating material and the third device prior to thecuring, the fourth device being one of a die and a wafer, wherein thecuring includes curing the third coating material such that the thirdcoating material transforms form the first state to a second statesubstantially the same as the first and second coating materials. Inother embodiments, the method further includes pre-treating the firstand second coating materials prior to the curing. In some embodiments,the pre-treating includes heating the first and second coating materialsto a temperature that is less than a curing temperature of the first andsecond coating materials. In other embodiments, the method furtherincludes post-treating the first and second coating materials after thecuring.

In some other embodiments, the step of providing the first coatingmaterial includes forming the first coating material on the firstdevice, and overlying the second device on the first coating materialand the first device, and the step of providing the second coatingmaterial includes forming the second coating material on the seconddevice, and overlying the third device on the second coating materialand the second device. In still other embodiments, the step of providingthe first coating material includes forming the first coating materialon the second device, and overlying the second device with the firstcoating material on the first device, and the step of providing thesecond coating material includes forming the second coating material onthe third device, and overlying the third device with the second coatingmaterial on the second device.

Also provided is a semiconductor device that includes a first device, asecond device overlying the first device and electrically coupled to thefirst device, a third device overlying the second device andelectrically coupled to the second device, a first coating materialdisposed between the first and second devices, and a second coatingmaterial disposed between the second and third devices, wherein thefirst and second coating materials are configured with substantiallysimilar thermal histories. In some embodiments, the first and secondcoating materials have substantially the same curing cycles. In otherembodiments, the first, second, and third devices are each one of a dieand a wafer. In some other embodiments, the method further includesproviding a fourth device, the fourth device being one of a die and awafer, providing a third coating material between the third device andthe fourth device, and the step of curing includes curing the thirdcoating material in the same process as the first and second coatingmaterials.

In still other embodiments, the first, second, and third devices eachinclude a plurality of through silicon via (TSV) structures. In someembodiments, one of the TSV structures of the first device iselectrically coupled to one of the TSV structures of the second device,and where one of the TSV structures of the second device is electricallycoupled to one of the TSV structures of the third device. In otherembodiments, the first device includes a plurality of conductive bumpsfor connecting to another semiconductor device. In some otherembodiments, the semiconductor device further includes a carriersubstrate for supporting a structure, and the first device overlies thecarrier substrate and is secured to the carrier substrate.

Additionally, a method for fabricating a stacked semiconductor device isprovided which includes providing a first device having a circuit and afirst coating material formed thereon, stacking a second device on thefirst coating material and the first device, the second device having acircuit and a second coating material formed thereon, stacking a thirddevice on second coating material and the second device, the thirddevice having a circuit, and performing one thermal process thatelectrically couples the circuits of the first, second, and thirddevices to form a circuit of the stacked semiconductor device. In someembodiments, the method further includes pre-treating the first andsecond coating materials prior to the one thermal process, where atemperature of the pre-treating is from about 80° C. to about 150° C. Insome other embodiments, the method further includes post-treating thefirst and second coating materials after the one thermal process, wherea temperature of the post-treating is from about 100° C. to about 200°C.

In still other embodiments, a temperature of the one thermal process isfrom about 200° C. to about 300° C. In other embodiments, the fourthdevice includes a third coating material formed thereon, the thirdcoating material substantially the same as the first and second coatingmaterials, the method further includes stacking a fifth device on thethird coating material and the fourth device, the fifth device being achip with a circuit, and the circuit of the fifth device is electricallycoupled to the circuit of the fourth device in response to the thermalprocess. In still other embodiments, the method further includesselecting the first and second coating materials to be one of a B-stagepolymer and a solid film.

Although embodiments of the present disclosure have been described indetail, those skilled in the art should understand that they may makevarious changes, substitutions and alterations herein without departingfrom the spirit and scope of the present disclosure. For example,although the embodiments disclosed herein uses TSV structures for chipand wafer packaging, it is understood that the methods may beimplemented in other traditional packaging technologies that do not useTSV structures. Accordingly, all such changes, substitutions andalterations are intended to be included within the scope of the presentdisclosure as defined in the following claims.

Several different advantages exist from these and other embodiments. Themethods and stacked semiconductor devices disclosed herein provide asimple and cost-effective technique for minimizing various defectsinduced by thermal stress in stacked semiconductor devices. Thus, theperformance and reliability of stacked semiconductor devices will beimproved. The curing/reflowing of the coating layers of the stackedsemiconductor device are performed in one thermal process. Accordingly,the fabrication of stacked semiconductor devices will take lessprocessing time, and fewer equipment will be used to complete a fullmultilayer process thereby reducing costs. The coating materialdisclosed herein may be configured as a lamination or tape such that itis easy to apply to devices before they are stacked and bonded togetherto form a stacked semiconductor device. Further, the methods and stackedsemiconductor devices disclosed herein may be implemented forchip-to-chip stacking, wafer-to-wafer stacking, and chip-to-waferstacking.

We claim:
 1. A semiconductor device comprising: a first device includinga first plurality of conductive bumps; a second device including asecond plurality of conductive bumps, the second device overlying thefirst device and electrically coupled to the first device; a thirddevice including a third plurality of conductive bumps, the third deviceoverlying the second device and electrically coupled to the seconddevice; a first coating material disposed between the first and seconddevices, wherein the first coating material continuously covers asurface area between and surrounding the second plurality of conductivebumps, and wherein a wall of the first coating material is in directcontact with a wall of the second plurality of conductive bumps; and asecond coating material disposed between the second and third devices,wherein the second coating material continuously covers a surface areabetween and surrounding the third plurality of conductive bumps, andwherein a wall of the second coating material is in direct contact witha wall of the third plurality of conductive bumps.
 2. The semiconductordevice of claim 1, wherein the first and second coating materials areconfigured with substantially similar defect characteristics.
 3. Thesemiconductor device of claim 1, wherein the first, second, and thirddevices are each dies.
 4. The semiconductor device of claim 3, furthercomprising a fourth device including a fourth plurality of conductivebumps, the fourth device overlying the third device and electricallycoupled to third device, the fourth device being a die; and a thirdcoating material disposed between the third and fourth devices, thethird coating material being configured with substantially similardefect characteristics as that of the first and second coatingmaterials, wherein the third coating material continuously covers asurface area between and surrounding the fourth plurality of conductivebumps, and wherein a wall of the third coating material is in directcontact with a wall of the fourth plurality of conductive bumps.
 5. Thesemiconductor device of claim 1, wherein the first, second, and thirddevices each include a plurality of through silicon via (TSV)structures.
 6. The semiconductor device of claim 5, wherein one of theTSV structures of the first device is electrically coupled to one of theTSV structures of the second device, and wherein one of the TSVstructures of the second device is electrically coupled to one of theTSV structures of the third device.
 7. The semiconductor device of claim1, wherein the second and third plurality of conductive bumps connectthe first, second, and third devices.
 8. The semiconductor device ofclaim 1, further comprising: a carrier substrate; and wherein the firstdevice overlies the carrier substrate and is secured to the carriersubstrate.
 9. A semiconductor device comprising: a first device having afirst through-silicon via (TSV) structure; a first coating materialdisposed over the first device, wherein the first coating materialcontinuously extends over the first device and covers the first TSVstructure; a second device disposed over the first device and within thefirst coating material, wherein the second device includes a second TSVstructure and a plurality of conductive bumps, wherein the plurality ofconductive bumps are positioned within the first coating material; asecond coating material disposed over the second device, wherein thesecond coating material continuously extends over the second device andcovers the second TSV structure; and a third device disposed over thesecond coating material, wherein the third device includes a third TSVstructure.
 10. The semiconductor device of claim 9, wherein the firstcoating material includes a polymer component and a flux component. 11.The semiconductor device of claim 9, wherein the first coating materialand the second coating material are substantially similar.
 12. Thesemiconductor device of claim 9, wherein at least one of the conductivebumps from the plurality of conductive bumps contacts the first TSVstructure.
 13. The semiconductor device of claim 9, wherein the first,second, and third devices each include a circuit; and wherein thecircuits of the first, second, and third devices are electricallycoupled using the first and second TSV structures.
 14. The semiconductordevice of claim 9, wherein the first, second, and third devices arechips.
 15. A semiconductor device comprising: a first device having afirst through-silicon via (TSV) structure; a first coating materialdisposed over the first device, the first coating material extendingover the first device and covering the first TSV structure; a seconddevice disposed on the first coating material, the second device havinga second TSV structure and a plurality of conductive bumps, wherein theplurality of conductive bumps are disposed within the first coatingmaterial; a second coating material disposed over the second device, thesecond coating material extending over the second device and coveringthe second TSV structure; and a third device disposed on the secondcoating material.
 16. The semiconductor device of claim 15, wherein thefirst TSV structure is exposed on a side of the first device.
 17. Thesemiconductor device of claim 15, wherein the second device furtherincludes a bonding pad, wherein the bonding pad is electrically coupledto the second TSV structure.
 18. The semiconductor device of claim 15,wherein the first coating material includes a B-stage polymer.
 19. Thesemiconductor device of claim 15, wherein the first coating materialcontinuously extends over the first device and the second coatingmaterial continuously extends over the second device.
 20. Thesemiconductor device of claim 15, wherein the first, second, and thirddevices are one of a circuit and a die, and wherein the first, second,and third devices are electrically coupled together.